Traditionally, a basic block diagram of a SRAM used in a read operation comprises a decoder 1, a RAM_Core 2, a controller 3, and a sense amplifier 4 (as shown in FIG. 1). The RAM_Core 2 comprises a plurality of arrays of memory cells. The controller 3 receives different signals such as an address signal or other circuit signals, and then outputs the signals to the decoder 1. The RAM_Core 2 receives a word line (WL) data, and outputs a bit_line (BL) data as well as a bit_line_bar (BLB) data to the sense amplifier 4. Once the sense amplifier 4 receives an effective sense amplifier enable (SAE) signal from the controller 3, it will output a read data of a memory cell.
FIG. 2 shows a timing diagram showing the read operation of the SRAM of FIG. 1. The WL signal is effective after a rising edge of a clock (CLK) signal with a fixed time delay. The BL/BLB signal starts to discharge after the WL signal is effective. After a differential voltage is setup on BL/BLB, the SAE signal is effective. Then, the read data of memory cell 0 (RD_M0) is available after a rising edge of the SAE signal with a fixed time delay.
FIG. 3 illustrates a block diagram of a 16 k*64 b SRAM used in a traditional read operation. The SRAM comprises a first array 16, a second array 17, a third array 18 and a fourth array 19 of memory cells, wherein each array of memory cells comprises memory cell 0, memory cell 1, memory cell 2, and memory cell 3. In FIG. 3, reference numerals 12, 13, 14 and 15 are used to show memory cell 0, memory cell 1, memory cell 2, and memory cell 3, respectively. A first 2-to-4 decoder 10 decodes address (ADR1) signals to generate selection signals SI<0>, SI<1>, SI<2>, and SI<3>. SI<0>, SI<1>, SI<2>, and SI<3> are inputted to a first 4-to-1 multiplexer 20. Four read data RD_M0<63:0>, RD_M1<63:0>, RD_M2<63:0>, and RD_M3<63:0> of memory cell 0, memory cell 1, memory cell 2, and memory cell 3 in the first array 16 of memory cells are inputted to the first 4-to-1 multiplexer 20. Then, the first 4-to-1 multiplexer 20 outputs a read data RD_P0<63:0> of the first array 16 of memory cells. Similarly, a second 4-to-1 multiplexer 21, a third 4-to-1 multiplexer 22, and a fourth 4-to-1 multiplexer 23, are used in turn to output read data RD_P1<63:0>, RD_P2<63:0>, and RD_P3<63:0> of the second array 17, the third array 18, and the fourth array 19 of memory cells.
In the same way, a second 2-to-4 decoder 11 decodes address (ADR2) signals to generate selection signals S<0>, S<1>, S<2>, and S<3>. S<0>, S<1>, S<2>, and S<3> are inputted to a fifth 4-to-1 multiplexer 24. The fifth 4-to-1 multiplexer 24 also receives read data RD_P0<63:0>, RD_P1<63:0>, RD_P2<63:0>, and RD_P3<63:0> from the outputs of the first 4-to-1 multiplexer 20, the second 4-to-1 multiplexer 21, the third 4-to-1 multiplexer 22, and the fourth 4-to-1 multiplexer 23, respectively. By selecting a particular selection signal, the fifth 4-to-1 multiplexer 24 outputs a read data RD<63:0> of the SRAM.
FIG. 4 illustrates a timing diagram showing the read operation of the traditional SRAM of FIG. 3. Since a rising edge of the selection signal SI<0> occurs before the stability of the read data RD_M0<0>, the read data RD_P0<0> between the rising edge of the selection signal SI<0> and the stability of the read data RD_M0<0> are invalid. A data bus will toggle for the above invalid data, and thus consumes power significantly. For the same reason, another unwanted toggle will subsequently occur for the invalid data of RD<0>.
FIG. 5 is a block diagram of a 16 k*64 b SRAM that employs a different data selection scheme. All read operations in FIG. 3 and FIG. 5 are the same except the generation of the selection signals. As illustrated in FIG. 5, an address decoding signal ADR_dec and a pulse are inputted to an AND gate so as to generate a selection signal.
FIG. 6 is a timing diagram showing a read operation of the SRAM of FIG. 5. A pulse 1 needs to be well designed, thereby making a rising edge of the pulse 1 occur after the stability of the read data RD_M0<0>. Due to the time delay of the AND gate, a rising edge of the selection signal SI<0> occurs after the rising edge of the pulse 1. Since the rising edge of the selection signal SI<0> occurs after the stability of the read data RD_M0<0>, the read data RD_P0<0> will not toggle.
Referring again to FIG. 6, likewise, a pulse 2 is well designed so that its rising edge occur after the stability of the read data RD_P0<0>. For the same reason, a rising edge of the selection signal S<0> occurs after the rising edge of the pulse 2. Again, since the rising edge of the selection signal S<0> occurs after the stability of the read data RD_P0<0>, the read data RD<0> will not toggle. In FIG. 6, if the rising edge of the selection signal SI<0> comes before the stability of the read data RD_M0<0>, an invalid data will occur on the read data RD_P0<0>. Similarly, if the rising edge of the selection signal S<0> comes before the stability of the read data RD_P0<0>, an invalid data will occur on the read data RD<0>. It is even worse that if the correct read data are not stable before a falling edge of the selection signal, the wrong data will be read out. Another problem in the traditional SRAM is that if the pulse is over designed to make it come later than the stability of the read data, the timing performance is sacrificed.